This invention is an electronic device with an LDO which provides a large dynamic range of the load current while having very low self power consumption.
The present invention is an electronic device having an LDO regulator for varying loads. The LDO regulator has a primary supply node coupled to a primary voltage supply and an output node providing a secondary supply voltage and a load current. A bias current source generates a bias current. A gain stage coupled to the bias current source increases the maximum available load current. The gain stage includes a first MOS transistor biased in weak inversion. This first MOS transistor is coupled to a current mirror mirroring the drain current through the first MOS transistor to an output node. Further, the gate source voltage of the first MOS transistor increases in response to a decreasing secondary supply voltage level at the output node to increase the available load current. The bias current generated by the bias current source drives the first MOS transistor. The drain current of the first MOS transistor is mirrored using the current mirror so that the current received at the output node is proportional to the bias current. When the voltage at the output node (the secondary supply voltage) decreases the gate source voltage of the first MOS transistor increases because the first MOS transistor is biased in weak inversion (i.e. the gate voltage applied to the first MOS transistor is less than its threshold voltage). The current mirrored from the first MOS transistor to the output node increases, which increases the size of the load current at the output node. In this way, the LDO regulator only needs a very low current (e.g. about 100 nA to 300 nA) for its own operation and yet is able to drive a current of several tens of μA (for example 30 μA) as load current when in low power mode (LPM). The present invention thus allows the lowest supply current to be used, but is also able to deliver load currents that are orders of magnitude higher than in the unloaded case.
Preferably, the first MOS transistor has a gate coupled to a constant reference voltage level and a source coupled to a first node. The voltage level of the first node drops in response to the decreasing secondary supply voltage level at the output node. Thus the secondary supply voltage level at the output node is fed back to the gain stage. This causes the voltage at the first node to decrease when the voltage level at the output node decreases. This causes the gate source voltage of the first MOS transistor to increase further.
The gain stage may include a second MOS transistor and a third MOS transistor. The gate of the second MOS transistor is coupled to the output node, with a source of the second MOS transistor and a drain of the third MOS transistor coupled to the first node. A drain of the second MOS transistor is coupled to the bias current source and a gate of the third MOS transistor is coupled to the drain of the second MOS transistor. The secondary supply voltage at the output node is then the voltage applied to the gate of the second MOS transistor. Thus, as the secondary supply voltage decreases, the gate voltage of the second MOS transistor decreases and the amount of current from the bias current source through the second MOS transistor decreases, leading to a voltage decrease at the first node.
The current mirror preferably comprises a diode connected fourth MOS transistor and a fifth MOS transistor having a gate coupled to a gate of the fourth MOS transistor and biased in weak inversion. A drain of the fourth MOS transistor is coupled to a drain of the first MOS transistor and a source of the fourth MOS transistor coupled to a resistive element such that the gate source voltage of the fifth MOS transistor corresponds to combined voltages of both the gate source voltage of the fourth MOS transistor and a voltage drop across the resistive element. The fourth and fifth MOS transistors then form the current mirror and mirror the current from the first MOS transistor to the output node.
In another aspect of the present invention includes a sixth MOS transistor. The gate of the third MOS transistor is coupled through the sixth MOS transistor to the drain of the third MOS transistor. A drain of the sixth MOS transistor is coupled to the gate of the third MOS transistor. A source of the sixth MOS transistor is coupled to the drain of the second MOS transistor. The source of the sixth MOS transistor is further coupled to a second bias current source. A gate of the sixth MOS transistor receives a constant voltage level. The sixth MOS transistor closes the feedback loop to the third MOS transistor without restrictions on the voltage input range and has a common gate configuration so that the dominant pole of the feedback loop will be at the gate of the third MOS transistor. The stability of the LDO circuit is then assured since all circuit loops are single pole only. Addition of the sixth MOS transistor to the feedback loop increases the voltage input range to the gain stage fed back from the output node.